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5.2.1 Channel Registers

5.2.1.7 Interrupt Mask Register

This register is used to specify which events should result in an interrupt asserted to the VMEbus.

Interrupt Mask Register
Channel Offset
Read/Write
76543210
$0FMF_Ua2MF_Ua1MF_DIMF_INDMCARMBORMDIMIND

MF_Ua2
When this bit is set, and the corresponding F_Ua2 bit in the Direct Input Register is set, an interrupt request to the Bus Interrupter Module (BIM) will be active.

MF_Ua1
When this bit is set, and the corresponding F_Ua1 bit in the Direct Input Register is set, an interrupt request to the Bus Interrupter Module (BIM) will be active.

MF_DI
When this bit is set, and the corresponding F_DI bit in the Direct Input Register is set, an interrupt request to the Bus Interrupter Module (BIM) will be active.

MF_IND
When this bit is set, and the corresponding F_IND bit in the Direct Input Register is set, an interrupt request to the Bus Interrupter Module (BIM) will be active.

MCAR
When this bit is set, and the corresponding CAR bit in the Index Status Register is set, then an interrupt request to the Bus Interrupter Module (BIM) will be active.

MBOR
When this bit is set, and the corresponding MOR bit in the Index Status Register is set, then an interrupt request to the Bus Interrupter Module (BIM) will be active.

MDI
When this bit is set, a difference between the DI bit and the CDI bit will cause an interrupt request to the Bus Interrupter Module (BIM).

MIND
When this bit is set, a difference between the IND bit and the CIND bit will cause an interrupt request to the Bus Interrupter Module (BIM).

After a SYSRESET these bits are cleared.


BI-0433 - 12 Channel Incremental Encoder Interface with Isolated Inputs and Cable Fault Detection - 23 MAY 1997 Copyright 1997 Brand Innovators B.V. [Next] [Previous] [Up] [Top] [Contents] [Back]