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5.2.1 Channel Registers
This register gives the status of several events that can occur.
Index Status Register
Channel Offset
Read Only | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| $07 | | | | | CAR | BOR | DIS | INDS |
- CAR
- This bit is set when a 32 bit carry has occurred. It signals a 32 bit counter over flow.
- BOR
- This bit is set when a 32 bit borrow has occurred. It signals a 32 bit counter under flow.
- DIS
- This bit is set when the digital input DI has been active.
- INDS
- When INDS=1, an index pulse has occurred. It can only be set when the EIND bit in the Enable Index Register is set.
All bits are cleared after the Index Status Register has been read.
BI-0433 - 12 Channel Incremental Encoder Interface with Isolated Inputs and Cable Fault Detection - 23 MAY 1997
Copyright © 1997 Brand Innovators B.V.
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