5.2.1 Channel Registers

5.2.1.2 Enable Index Register

Enable Index Register

Channel Offset Read/Write	7	6	5	4	3	2	1	0
$05							LVLIND	EIND

EIND

When EIND=1, an index pulse will reset the counter.
When EIND=0, the index pulse is masked and will not reset the counter.

LVLIND

When LVLIND=0, a '1-0-1' pulse on the index input will clear the counter, if enabled using EIND.
When LVLIND=1, a '0-1-0' pulse on the index input will clear the counter, if enabled using EIND.

Note: The state of the EIND bit does not affect the interrupt capability of the index input.