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5.2.1 Channel Registers Compare State Register

This register specifies the levels the digital input signals will be compared to.

Compare State Register
Channel Offset
$0B      CDICIND

When the digital inputs differ from the values of CDI and CIND written in this register, an interrupt can be generated and a sample of the digital inputs is made in the State On Interrupt Register.

After an interrupt is generated due to a change of state, a write access to the Compare State Register must be performed before another interrupt can be generated in the specific group. The write access to the Compare State Register will clear the interrupt request to the BIM. If the IRE bit in the Group BIM Control Register is set before the Compare State Register is written, another interrupt will be generated.

BI-0433 - 12 Channel Incremental Encoder Interface with Isolated Inputs and Cable Fault Detection - 23 MAY 1997 Copyright 1997 Brand Innovators B.V. [Next] [Previous] [Up] [Top] [Contents] [Back]