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5.2 Device Group Registers

5.2.5 Group BIM Control Register

This register is used to set different options for the BIM.

Group BIM Control Register
Group Offset
Read/Write
76543210
$3BFFACX/INIREIRACL2L1L0

L2, L1, L0
Interrupt level. These bits determine the level at which an interrupt will be generated. A value of zero disables the interrupt.

IRAC
Interrupt Auto Clear. If the IRAC bit is set, IRE is cleared during an interrupt acknowledge cycle responding to this request. This action of clearing IRE disables the interrupt request. To re-enable the interrupt associated with this register, IRE must be set again by writing to the Group BIM Control Register.

IRE
Interrupt Enable. This bit must be set to enable the bus interrupt request associated with this register. Thus, if the interrupt input line is asserted and IRE is cleared, no interrupt request will be asserted.

X/IN
External/Internal.
When this bit is cleared, the Interrupt Vector from the Group BIM Vector Register is presented on the data lines during an interrupt acknowledge cycle.
When this bit is '1', the BIM does not supply the vector.

Note: The X/IN must always be programmed to 0 because there is no other on-board vector source.

FAC
Flag Auto Clear. If the FAC bit is set, the Flag bit is automatically cleared during an interrupt acknowledge cycle.

F
Flag. Bit 7 is a flag that can be used in conjunction with the test and set instruction of the MC680xx. It can be changed without affecting BIM operation.


BI-0433 - 12 Channel Incremental Encoder Interface with Isolated Inputs and Cable Fault Detection - 23 MAY 1997 Copyright 1997 Brand Innovators B.V. [Next] [Previous] [Up] [Top] [Contents] [Back]